Modern electronic computing systems, such as microprocessor systems, typically include a processor and datapath configured to receive and process instructions. Generally, instructions are either “simple” or “complex.” Typical simple instructions encompass a single operation, such as, for example, a load or store from memory. Common Reduced Instruction Set Computers (RISC) employ simple instructions exclusively. Complex instructions typically encompass more than one single operation, such as an add/store, for example. Common Complex Instruction Set Computers (CISC) employ complex instructions and sometimes also employ simple instructions. Both simple and complex instructions are subject to dependencies.
Generally, a dependency occurs where an instruction requires data from sources that are themselves the result of another instruction. For example, in the instruction sequence:
ADD $8, $7, $5
SW $9, (0)$8
The ADD (add) instruction adds the contents of register $7 to the contents of register $5 and puts the result in register $8. The SW (store word) instruction stores the contents of register $9 at the memory location address found in $8. As such, the SW instruction must wait for the ADD instruction to complete before storing the contents of register $8. The SW instruction therefore has a dependency on the ADD instruction. The illustrated dependency is also known as a read-after-write (RAW) dependency.
One common approach to tracking dependencies is a “dependency matrix,” such as that described in U.S. Pat. Nos. 6,065,105 and 6,334,182. Generally, a conventional dependency matrix includes rows and columns. Each bit or element, i.e., the intersection of one row and one column, corresponds to a dependency of an instruction in the issue queue. Each instruction in the issue queue is associated with a particular row in the dependency matrix, with the read-after-write (RAW) dependencies noted by bits set on a given column within that row.
As a given resource becomes available, the dependency matrix clears the column associated with that resource, setting all locations in the column to zero. Once a given instruction (row) has all of its RAW dependencies resolved, i.e. once all columns in that row have been set to zero, then the instruction is ready to issue.
As new instructions enter the issue queue, allocation logic assigns the new instructions to a position within the dependency matrix. The dependency matrix logic checks sources for that instruction against a destination register file. A match between an entering instruction's source and a pending instruction's destination indicates that the entering instruction is dependent on the pending entry, and the dependency matrix logic sets the bit in the appropriate position in the dependency matrix. The newly entered instruction will not issue from the issue queue until after the instruction on which it depends has issued, as indicated by the dependency matrix.
Conventional dependency matrices can only handle an instruction that needs to issue only once. This limits the speed and functionality of a system using conventional dependency matrices, because an instruction that needs to be utilized multiple times must be reinserted into the dependency matrix each time the instruction is needed. This increases the total time necessary to execute the instruction.
For example, as described above, complex instructions involve multiple parts. In systems using conventional dependency matrices, these instructions must be cracked into separate instructions, assigning each resultant separate instruction to a separate position within the dependency matrix and the issue queue, thereby limiting the quantity of instructions that can be issued in a given time period by the dependency matrix. Further, cracking the instruction requires that the dependency matrix be overwritten for the second instruction. Additionally, the system must perform extra source-completion compares in order to execute the second instruction, which also increases the time and power required to execute the original instruction.
Therefore, there is a need for a system and/or method for double issuing instructions using a dependency matrix that addresses at least some of the problems and disadvantages associated with conventional systems and methods.